[[["容易理解","easyToUnderstand","thumb-up"],["確實解決了我的問題","solvedMyProblem","thumb-up"],["其他","otherUp","thumb-up"]],[["缺少我需要的資訊","missingTheInformationINeed","thumb-down"],["過於複雜/步驟過多","tooComplicatedTooManySteps","thumb-down"],["過時","outOfDate","thumb-down"],["翻譯問題","translationIssue","thumb-down"],["示例/程式碼問題","samplesCodeIssue","thumb-down"],["其他","otherDown","thumb-down"]],["上次更新時間:2025-07-27 (世界標準時間)。"],[],[],null,["# VSync\n\nThe VSync signal synchronizes the display pipeline. The display\npipeline consists of app rendering, SurfaceFlinger composition, and the Hardware\nComposer (HWC) presenting images on the display. VSync synchronizes the\ntime apps wake up to start rendering, the time SurfaceFlinger wakes up to\ncomposite the screen, and the display refresh cycle. This synchronization\neliminates stutter and improves the visual performance of graphics.\n\nThe HWC generates VSync events and sends the events to SurfaceFlinger through\nthe callback: \n\n```carbon\ntypedef void (*HWC2_PFN_VSYNC)(hwc2_callback_data_t callbackData,\n hwc2_display_t display, int64_t timestamp);\n```\n| **Note:** The HWC triggers `hwc2_callback_data_t` from a thread of `HAL_PRIORITY_URGENT_DISPLAY` with as little latency as possible, typically less than 0.5 ms.\n\nSurfaceFlinger controls whether or not the HWC generates VSync events by\ncalling to `setVsyncEnabled`. SurfaceFlinger enables\n`setVsyncEnabled` to generate VSync events so it can synchronize with\nthe refresh cycle of the display. When SurfaceFlinger is synchronized to the\ndisplay refresh cycle, SurfaceFlinger disables `setVsyncEnabled` to\nstop the HWC from generating VSync events. If SurfaceFlinger detects a\ndifference between the actual VSync and the VSync it previously established\nSurfaceFlinger re-enables VSync event generation.\n\nVSync offsets\n-------------\n\nThe sync app and SurfaceFlinger render loops to the\nhardware VSync. On a VSync event, the display begins showing frame *N* while\nSurfaceFlinger begins compositing windows for frame *N+1* . The app handles\npending input and generates frame *N+2*.\n\nSynchronizing with VSync delivers consistent latency. It reduces errors in\napps and SurfaceFlinger and minimizes displays drifting in and out of phase with\neach other. This assumes app and SurfaceFlinger per-frame\ntimes don't vary widely. The latency is at least two frames.\n\nTo remedy this, you can employ VSync offsets to reduce the input-to-display\nlatency by making app and composition signal relative to hardware\nVSync. This is possible because app plus composition usually takes less\nthan 33 ms.\n\nThe result of a VSync offset is three signals with same period and offset\nphase:\n\n- `HW_VSYNC_0` --- Display begins showing next frame.\n- `VSYNC` --- App reads input and generates next frame.\n- `SF_VSYNC` --- SurfaceFlinger begins compositing for next frame.\n\nWith VSync offsets, SurfaceFlinger receives the buffer and composites the\nframe while the app simultaneously processes the input and renders\nthe frame.\n| **Note:** VSync offsets reduce the time available for app and composition, providing a greater chance for error.\n\nDispSync\n--------\n\nDispSync maintains a model of the periodic hardware-based VSync events of a\ndisplay and uses that model to execute callbacks at specific phase\noffsets from the hardware VSync events.\n\nDispSync is a software phase-lock loop (PLL) that generates the\n`VSYNC` and `SF_VSYNC` signals used by Choreographer and SurfaceFlinger,\neven if not offset from hardware VSync.\n\nThe DispSync flow is illustrated in the following figure:\n\n**Figure 1.** DispSync flow.\n\nDispSync has the following qualities:\n\n- *Reference* --- `HW_VSYNC_0`.\n- *Output* --- `VSYNC` and `SF_VSYNC`.\n- *Feedback* --- Retire fence signal timestamps from the HWC.\n\nVSync retire offsets\n--------------------\n\nThe signal timestamp of retire fences must match HW VSync, even on devices\nthat don't use the offset phase. Otherwise, errors appear to be more severe\nthan they are. Smart panels often have a delta where the retire fence is the end\nof direct memory access (DMA) to display memory, but the actual display switch\nand HW VSync is some time later.\n\n`PRESENT_TIME_OFFSET_FROM_VSYNC_NS` is set in the device's\n`BoardConfig.mk` makefile. It's based on the display controller and panel\ncharacteristics. The time from the retire fence timestamp to the HW VSync\nsignal is measured in nanoseconds.\n\nVSYNC and SF_VSYNC offsets\n--------------------------\n\n`VSYNC_EVENT_PHASE_OFFSET_NS` and\n`SF_VSYNC_EVENT_PHASE_OFFSET_NS` are set conservatively based on\nhigh-load use cases, such as partial GPU composition during window transition\nor Chrome scrolling through a web page containing animations. These offsets\nallow for long app render time and long GPU composition time.\n\nMore than a millisecond or two of latency is noticeable. To minimize latency\nwithout significantly increasing error counts, integrate thorough automated error\ntesting.\n| **Note:** `VSYNC` and `SF_VSYNC` offsets are also configured in the device's `BoardConfig.mk` file. Both settings are offset in nanoseconds after `HW_VSYNC_0`, default to zero (if not set), and can be negative."]]